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10 November 2007 The GPS code acquisition based on pipelined FFT processor
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Proceedings Volume 6795, Second International Conference on Space Information Technology; 67956D (2007) https://doi.org/10.1117/12.775258
Event: Second International Conference on Spatial Information Technology, 2007, Wuhan, China
Abstract
This paper describes one implementation of the long PN codes acquisition especially for GPS P(Y) code direct acquisition. The design method is based on the parallel method using the ultra long FFT (Fast Fourier Transform) based processing which searches over time uncertainty in parallel and frequency uncertainty serially. The FFT processor is based on R22SDF (single-path delay feedback) pipelined FFT architecture for its least memory use. The design was implemented with the FPGA device, and is tested and verified with the simulated GPS P code. The system can search in less than 60 seconds over 2.5 KHz of frequency uncertainty and 1 sec of time uncertainty with the work speed higher than 100MHz.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Wei Li, Haibing Zhu, Jun Wang, and Shaohong Li "The GPS code acquisition based on pipelined FFT processor", Proc. SPIE 6795, Second International Conference on Space Information Technology, 67956D (10 November 2007); https://doi.org/10.1117/12.775258
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