21 December 2007 Patterning techniques for next generation IC's
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Abstract
Reduction of linear critical dimensions (CDs) beyond 45 nm would require significant increase of the complexity of pattern definition process. In this work, we discuss the key successor methodology to the current optical lithography, the Double Patterning Technique (DPT). We compare the complexity of CAD solutions, fab equipment, and wafer processing with its competitors, such as the nanoimprint (NIL) and the extreme UV (EUV) techniques. We also look ahead to the market availability for the product families enabled using the novel patterning solutions. DPT is often recognized as the most viable next generation lithography as it utilizes the existing equipment and processes and is considered a stop-gap solution before the advanced NIL or EUV equipment is developed. Using design for manufacturability (DfM) rules, DPT can drive the k1 factor down to 0.13. However, it faces a variety of challenges, from new mask overlay strategies, to layout pattern split, novel OPC, increased CD tolerances, new etch techniques, as well as long processing time, all of which compromise its return on investment (RoI). In contrast, it can be claimed e.g., that the RoI is the highest for the NIL but this technology bears significant risk. For all novel patterning techniques, the key questions remain: when and how should they be introduced, what is their long-term potential, when should they be replaced, and by what successor technology. We summarize the unpublished results of several panel discussions on DPT at the recent SPIE/BACUS conferences.
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A. Balasinski, "Patterning techniques for next generation IC's", Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 679803 (21 December 2007); doi: 10.1117/12.758963; https://doi.org/10.1117/12.758963
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