29 February 2008 Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors
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Proceedings Volume 6816, Sensors, Cameras, and Systems for Industrial/Scientific Applications IX; 68160D (2008); doi: 10.1117/12.777641
Event: Electronic Imaging, 2008, San Jose, California, United States
Abstract
A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.
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Shoji Kawahito, Shinya Itoh, "Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors", Proc. SPIE 6816, Sensors, Cameras, and Systems for Industrial/Scientific Applications IX, 68160D (29 February 2008); doi: 10.1117/12.777641; https://doi.org/10.1117/12.777641
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KEYWORDS
Amplifiers

CMOS sensors

Capacitors

Interference (communication)

Capacitance

Transistors

Cadmium sulfide

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