21 November 2007 The contact hole solutions for future logic technology nodes
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Abstract
The authors will explore the possible contact hole lithography solutions for the future technology nodes, from 90 nm down to 32 nm half-pitch (HP) in this paper. The special emphasis will be on the logic application because of the lack of a strong resolution enhancement technique (RET) for the random hole layouts. The use of illumination optimization, focus drilling can extend the projection optical lithography down to near 60 nm HP. The adoption of pitch split double exposure technique is needed to provide a robust manufacturing process window to further extend to around 50 nm HP. To further shrinking the design rule, a double patterning is need after the pitch split. The pitch split double patterning technique reaches its limit around 40 - 45 nm HP. The desire to not limit the integrated circuit (IC) design requires the lithography process k1 to be as high as possible. The random logic contact hole application is well suited for EUV lithography for 35 nm HP and below because of the high k1 process and a potential for high productivity of a mask based lithography. The pattern density of contact hole masks would not require a stringent mask defect requirement, and moreover, the EUV's relatively higher system flare does not have a significant impact on imaging. Actual EUV data and calibrated simulations will be used to demonstrate that EUV can provide a robust process window.
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Alek Chen, Steve Hansen, Marco Moers, Jason Shieh, Andre Engelen, Koen van Ingen Schenau, Shih-en Tseng, "The contact hole solutions for future logic technology nodes", Proc. SPIE 6827, Quantum Optics, Optical Data Storage, and Advanced Microlithography, 68271O (21 November 2007); doi: 10.1117/12.760197; https://doi.org/10.1117/12.760197
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