13 February 2008 Process flow innovations for photonic device integration in CMOS
Author Affiliations +
Abstract
Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mark Beals, Mark Beals, J. Michel, J. Michel, J. F. Liu, J. F. Liu, D. H. Ahn, D. H. Ahn, D. Sparacin, D. Sparacin, R. Sun, R. Sun, C. Y. Hong, C. Y. Hong, L. C. Kimerling, L. C. Kimerling, A. Pomerene, A. Pomerene, D. Carothers, D. Carothers, J. Beattie, J. Beattie, A. Kopa, A. Kopa, A. Apsel, A. Apsel, M. S. Rasras, M. S. Rasras, D. M. Gill, D. M. Gill, S. S. Patel, S. S. Patel, K. Y. Tu, K. Y. Tu, Y. K. Chen, Y. K. Chen, A. E. White, A. E. White, } "Process flow innovations for photonic device integration in CMOS", Proc. SPIE 6898, Silicon Photonics III, 689804 (13 February 2008); doi: 10.1117/12.774576; https://doi.org/10.1117/12.774576
PROCEEDINGS
14 PAGES


SHARE
RELATED CONTENT

A 30 GHz silicon photonic platform
Proceedings of SPIE (May 07 2013)
Silicon photonics and challenges for fabrication
Proceedings of SPIE (March 21 2017)
Micro/nano scale silicon based photonic devices
Proceedings of SPIE (November 26 2007)
Advances in fully CMOS integrated photonic devices
Proceedings of SPIE (February 09 2007)

Back to Top