26 February 2008 40-Gbps monolithically integrated transceivers in CMOS photonics
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Abstract
We report on the development of single-chip, monolithically-integrated 40 Gbps transceivers built in a 130 nm SOI CMOS process as part of Phase II of the DARPA EPIC program. In this talk we give an overview of the system architecture, including the transmit and receive paths as well as the control systems. We report on the performance of the individual building blocks, and discuss a scaling to 100 Gbps and beyond single-chip transceivers built in CMOS photonics.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
T. Pinguet, B. Analui, G. Masini, V. Sadagopan, S. Gloeckner, "40-Gbps monolithically integrated transceivers in CMOS photonics", Proc. SPIE 6898, Silicon Photonics III, 689805 (26 February 2008); doi: 10.1117/12.766865; https://doi.org/10.1117/12.766865
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