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13 February 2008 Power efficient photonic networks on-chip
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Abstract
The emerging class of multicore architectures and chip multiprocessors (CMPs) has fundamentally shifted the impact of communications on computing systems performance. Global communications at all scales is playing a central and dominant role in the ultimate realization of CMP system performance as it falls increasingly on the efficiency of the information exchange among the vastly growing number of compute and memory resources. In this new communication-bound paradigm, the realization of a system-wide scalable communications infrastructure that can meet the enormous bandwidths, capacities, and stringent latency requirements in an energy efficient manner is a key goal for scaling future computation performance. We explore how recent extraordinary advances in nanoscale silicon photonic technologies can be exploited for developing optical interconnection networks that address the critical bandwidth and power challenges presented across several levels of the CMP computing system communications infrastructure. Unlike prior generations of photonic technologies, the remarkable capabilities of nanoscale "CMOS photonics" offer the possibility of creating highly integrated platforms for generating and receiving optical signals with fundamentally superior power efficiencies. Optical interconnection network architectures employing these silicon nanophotonic building blocks are uniquely co-developed and explored in the context of bandwidth-driven computing models. The design of an on-chip optical interconnection network that employs nanoscale CMOS photonic devices and enables seamless off-chip communications to other CMP computing nodes and to external memory is described.
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Keren Bergman and Luca Carloni "Power efficient photonic networks on-chip", Proc. SPIE 6898, Silicon Photonics III, 689813 (13 February 2008); https://doi.org/10.1117/12.764901
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