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20 March 2008 EBDW technology for EB shuttle at 65nm node and beyond
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Abstract
When manufacturing prototype devices or low volume custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We attempt to apply EBDW mainly to critical interconnect layers to reduce the mask expenditure for the reason of technical output reusability. For 65nm node production, new 300mm EB direct writer had been installed. The process technologies have also been developing to meet sufficient qualities and productivities.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
T. Maruyama, M. Takakuwa, Y. Kojima, Y. Takahashi, K. Yamada, J. Kon, M. Miyajima, A. Shimizu, Y. Machida, H. Hoshino, H. Takita, S. Sugatani, and H. Tsuchikawa "EBDW technology for EB shuttle at 65nm node and beyond", Proc. SPIE 6921, Emerging Lithographic Technologies XII, 69210H (20 March 2008); https://doi.org/10.1117/12.772469
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