22 March 2008 Using in-chip overlay metrology
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Abstract
Overlay process control up to and including the 45nm node has been implemented using a small number of large measurement targets placed in the scribe lines surrounding each field. There is increasing concern that this scheme does not provide sufficiently accurate information about the variation of overlay within the product area of the device. These concerns have led to the development of new, smaller targets designed for inclusion within the device area of real products [1,2]. The targets can be as small as 1-3μm on a side, which is small enough to permit their inclusion inside the device pattern of many products. They are measured using a standard optical overlay tool, and then calibrated. However, there is a tradeoff between total measurement uncertainty (TMU) and target size reduction [1]. Also the calibration scheme applied impacts TMU. We report results from measurements of 3μm targets on 45nm production wafers at both develop and etch stages. An advantage of these small targets is that at the etch stage they can readily be measured using a SEM, which provides a method for verifying the accuracy of the measurements. We show how the 3μm in-chip targets can be used to obtain detailed information for in-device overlay variability and to maintain overlay control in successive process generations.
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Stefanie Girol-Gunia, Stefanie Girol-Gunia, Bernd Schulz, Bernd Schulz, Nigel Smith, Nigel Smith, Lewis Binns, Lewis Binns, } "Using in-chip overlay metrology", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69220N (22 March 2008); doi: 10.1117/12.774507; https://doi.org/10.1117/12.774507
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