22 March 2008 Improvement of gate CD uniformity for 55 nm node logic devices
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Abstract
This paper examines improvement in post-etching gate critical dimension (CD) uniformity by post exposure bake (PEB) temperature control. Although intra-wafer and inter-wafer resist CD uniformity is improved by PEB temperature optimization, intra-wafer gate CD uniformity after etching could not be improved due to etcher-attributed factors. To improve these factors, we carried out two-step optimization that combines lithography CD optimization with etching CD optimization. By using this method, the optimization strategy can clarify the targets of optimization in each step. PEB temperature optimization was performed by two step optimization in which etcher-attributed CD variations were canceled out, leading to 66% improvement of gate etching CD uniformity successfully. Without any changes in modification parameter, this PEB temperature optimization proved to be applicable to several reticle patterns with different pattern density. Moreover, this optimization method proved the applicability to the gate process for a 55nm node logic device for the duration of five months without modification. The result proved its long-term stability and practicality.
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Takashi Murakami, Taisaku Nakata, Kensuke Taniguchi, Takayuki Uchiyama, Megumi Jyousaka, Masahide Tadokoro, Yoshitaka Konishi, "Improvement of gate CD uniformity for 55 nm node logic devices", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 692210 (22 March 2008); doi: 10.1117/12.771548; https://doi.org/10.1117/12.771548
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