24 March 2008 Overlay improvement by zone alignment strategy
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Proceedings Volume 6922, Metrology, Inspection, and Process Control for Microlithography XXII; 69221G (2008); doi: 10.1117/12.772520
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States
Abstract
It is evident that DRAM ground rule continues to shrink down to 90nm and beyond, overlay performance has become more and more critical and important. Wafer edge shows different behavior from center by processes, e.g. a tremendous misalignment at wafer edge makes yield loss . When a conventional linear model is used for alignment correction, higher uncorrectable overlay residuals mostly happen at wafer edge. Therefore, it's obviously necessary to introduce an innovational alignment correction methdology to reduce unwanted wafer edge effect. In this study, we demonstrate the achievement of moderating poor overlay in wafer edge area by a novel zone-dependent alignment strategy, the so-called "Zone Alignment (ZA)". The main difference between the conventional linear model and zone alignment strategy is that the latter compensates an improper averaging effect from first modeling through weighting all surrounding marks with a nonlinear model. In addition, the effects of mark quantity and sampling distribution from "Zone Alignment" are also introduced in this paper. The results of this study indicate that ZA can reduce uncorrectable overlay residual and improve wafer-to-wafer variation significantly. Furthermore, obvious yield improvement is verified by ZA strategy. In conclusion, Zone alignment is the noteworthy strategy for overlay improvement. Moreover, suitable alignment map and mark numbers should be taken into consideration carefully when ZA is applied for further technology node.
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Chun-Yen Huang, Ai-Yi Lee, Chiang-Lin Shih, Richer Yang, Michael Yuan, Henry Chen, Ray Chang, "Overlay improvement by zone alignment strategy", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69221G (24 March 2008); doi: 10.1117/12.772520; https://doi.org/10.1117/12.772520
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KEYWORDS
Optical alignment

Semiconducting wafers

Yield improvement

Front end of line

Lithography

Overlay metrology

Process control

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