The effects of Line Width Roughness (LWR) on transistor performance are one of the hottest issues in semiconductor
industry. However, in most related studies, LWR is considered as the fluctuations of gate lengths and not of resist lines.
In this paper, we examine the direct effects of one of the spatial resist LWR parameters, the fractal dimension, on
transistor off current deviations for various correlation lengths and gate widths. The aim is to exploit the fractality of
LWR in order to link the gap between the LWR of long resist lines and the gate length roughness that affects transistor
performance. The used methodology is based on the simulation of both resist lines and transistor operation. The results
of the two step methodology are presented for both narrow and wide gates. For the first, it is found that for all correlation
lengths, higher fractal dimension (smaller roughness exponent) of the resist line leads to off state currents closer to the
nominal value. For wide gates, an interesting differentiation is found at the dependence of the standard deviation from
the fractal dimension as correlation length decreases. For sufficiently low correlation length, the behavior is reversed and
the low fractal dimension are more beneficial that the higher ones. An explanation of that reverse is provided by means
of the dependence of the CD variation on gate width for various fractal dimensions. Finally, the implications of these
findings on the dependencies of the yield of transistors on fractal dimension and correlation length are also discussed.