Paper
25 March 2008 Wafer edge polishing process for defect reduction during immersion lithography
Motoya Okazaki, Raymond Maas, Sen-Hou Ko, Yufei Chen, Paul Miller, Mani Thothadri, Manjari Dutta, Chorng-Ping Chang, Abraham Anapolsky, Chris Lazik, Yuri Uritsky, Martin Seamons, Deenesh Padhi, Wendy Yeh, Stephan Sinkwitz, Chris Ngai
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Abstract
The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Motoya Okazaki, Raymond Maas, Sen-Hou Ko, Yufei Chen, Paul Miller, Mani Thothadri, Manjari Dutta, Chorng-Ping Chang, Abraham Anapolsky, Chris Lazik, Yuri Uritsky, Martin Seamons, Deenesh Padhi, Wendy Yeh, Stephan Sinkwitz, and Chris Ngai "Wafer edge polishing process for defect reduction during immersion lithography", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69223A (25 March 2008); https://doi.org/10.1117/12.773113
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CITATIONS
Cited by 4 scholarly publications.
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KEYWORDS
Semiconducting wafers

Polishing

Immersion lithography

Particles

Lithography

Inspection

Surface finishing

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