25 March 2008 Scatterometry based overlay metrology
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Proceedings Volume 6922, Metrology, Inspection, and Process Control for Microlithography XXII; 69223L (2008); doi: 10.1117/12.768906
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States
Abstract
With the advancement of lithography, the overlay budget is becoming extremely tight. As the accuracy of overlay is important for achieving a good yield, the demand for the accuracy of overlay is ever increasing. According to the International Technology Roadmap for Semiconductors (ITRS), the overlay control budget for the 32nm technology node will be 5.7nm. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further technology development is required to bring it to this level. Especially for exposure tool inspection (e.g. alignment, overlay, wafer stage and distortion), more high accuracy should be required using 'resist to resist' pattern. In this work we simulated the measurement sensitivity for two types of scatterometry based overlay metrology, one is differential signal scatterometry overlay (SCOL), the other is double exposure type (DET).
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Takahiro Matsumoto, Hideki Ina, Koichi Sentoku, Satoru Oishi, "Scatterometry based overlay metrology", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69223L (25 March 2008); doi: 10.1117/12.768906; https://doi.org/10.1117/12.768906
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KEYWORDS
Overlay metrology

Scatterometry

Optical alignment

Inspection

Lithography

Semiconductors

Silicon

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