Paper
4 April 2008 Process manufacturability evaluation for next generation immersion technology node
M. Enomoto, T. Shimoaoki, T. Otsuka, S. Hatakeyama, K. Nafus, R. Naito, Y. Terashita, T. Shibata, H. Kosugi, M. Jyousaka, J. Mallmann, R. Maas, M. Blanco Mantecon, E. van Setten, J. Finders, S. Wang, C. Zoldesi
Author Affiliations +
Abstract
In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process manufacturability performance of the CLEAN TRACKTM LITHIUS ProTM-i/ TWINSCANTM XT:1900Gi lithocluster at the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUSTM i+/TWINSCAN XT:1700i. 1 In this work, process performance with regards to critical dimension uniformity and defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
M. Enomoto, T. Shimoaoki, T. Otsuka, S. Hatakeyama, K. Nafus, R. Naito, Y. Terashita, T. Shibata, H. Kosugi, M. Jyousaka, J. Mallmann, R. Maas, M. Blanco Mantecon, E. van Setten, J. Finders, S. Wang, and C. Zoldesi "Process manufacturability evaluation for next generation immersion technology node", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 69231W (4 April 2008); https://doi.org/10.1117/12.772552
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KEYWORDS
Semiconducting wafers

Critical dimension metrology

Manufacturing

Inspection

Bridges

Scanners

Standards development

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