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26 March 2008 Double patterning study with inverse lithography
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Pattern reduction has created a great deal of interest in finding effective methods to reduce the feature sizes of microelectronic and data-storage devices. These methods are divided between top-down approach such as photolithography and bottom-up approach such as self-assembly. For below 32 nm node technology, top-down approach has obstacles such as diffraction-limited resolution and high cost of ownership. Bottom-up approach has obstacles such as the insufficient support of processes and mass production. As one of solutions, double patterning technology (DPT) has been researched. In this paper, DPT is analytically shown more dense patterns then single or double exposures. For the reduction of the DPT complexity, a mask design method, which is the inverse lithography technology (ILT) based on pixels and the lithography model, is described as an integrated computational lithography platform to handle the DPT. The ILT can use the decomposition of design and optical proximity correction for below 32 nm half pitch pattern generation. A simple example is performed for its verification.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sang-Kon Kim "Double patterning study with inverse lithography", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 692323 (26 March 2008);

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