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26 March 2008 Sub-45nm resist process using stacked-mask process
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Abstract
The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems arise in the conventional S-MAP: 1) the deformation of SOC line pattern during SiO2 reactive ion etching (RIE), 2) the degradation of lithography performance due to high reflectivity at the interface between resist and SOG in high NA. In this study, we clarified the origin of the above problems and improved S-MAP materials and processes. Firstly, we found that the pattern deformation is induced by the inner stress due to volume expansion by fluorination during RIE, and that the deformation is suppressed by decreasing hydrogen content of SOC. Secondly, we developed new carbon-containing SOG that coexists with low reflectivity and acceptable etching performance. Using the above SOG and SOC, we developed a new S-MAP that shows an excellent lithography / etching performance in sub-45nm device fabrication.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yuriko Seino, Katsutoshi Kobayashi, Koutaro Sho, Hirokazu Kato, Seiro Miyoshi, Keisuke Kikutani, Junko Abe, Hisataka Hayashi, Tokuhisa Ohiwa, Yasunobu Oonishi, and Shinichi Ito "Sub-45nm resist process using stacked-mask process", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 69232O (26 March 2008); https://doi.org/10.1117/12.771840
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