7 March 2008 Enabling technology scaling with "in production" lithography processes
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Abstract
As the industry hits a road block with RETs that attempt to aggressively scale k1, we propose to extend the life of optical lithography by a complete co-optimization between circuit choices, layout patterns and lithography. We demonstrate that the judicious selection of a small number of layout patterns along with the appropriate circuit topologies would not only enable k1 relaxation but also efficient implementation of circuits. Additionally, in this paper, we discuss the use of regular design fabrics to extend the life of current generation lithography equipment. We will introduce the Front End of Line (FEOL) limited regular design fabric. The metal 1 patterns for this fabric are selected such that we can utilize a 1.2 NA 32nm metal 1 lithography process without any area penalty with respect to standard cells with conventional design rules, which require a 32nm metal 1 process with a rather unrealistic k1 of 0.35 while using a more advanced 1.35 NA tool. We also demonstrate simulation results on 2-dimensional layout patterns. The results suggest that smart selection of layout patterns can enable the extension of single exposure lithography to a 32nm production lithography process.
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Tejas Jhaveri, Tejas Jhaveri, Andrzej Strojwas, Andrzej Strojwas, Larry Pileggi, Larry Pileggi, Vyachelav Rovner, Vyachelav Rovner, } "Enabling technology scaling with "in production" lithography processes", Proc. SPIE 6924, Optical Microlithography XXI, 69240K (7 March 2008); doi: 10.1117/12.776484; https://doi.org/10.1117/12.776484
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