7 March 2008 45nm and 32nm half-pitch patterning with 193nm dry lithography and double patterning
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Double patterning technique is listed as the top option for 32nm technology nodes at recently updated 2007 International Technology Roadmap Semiconductor (ITRS). Double patterning (DP) effectively reduces the k1 factor to less than 0.25, however, various process challenges, including critical dimension uniformity (CDU), line edge and line width roughnesses (LER/LWR), and overlay, have to come up with solutions for the industry in device manufacturing. In this study, we developed a metal hard mask and a universal dual hard mask double patterning process and demonstrated 45nm half-pitch in dark field patterning and 32nm half pitch in bright field applications by using a 0.93NA 193nm dry scanner system. By using the optimized hard mask films and Applied Materials' Advanced Patterning Film (APFTM) as a bottom hard mask, the universal dual hard mask double patterning scheme shows significant improvement in line edge roughness and line width roughness, achieved best results of 2nm LER and 2.5nm LWR at APF hard mask.
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Huixiong Dai, Huixiong Dai, Chris Bencher, Chris Bencher, Yongmei Chen, Yongmei Chen, Hyungje Woo, Hyungje Woo, Chris Ngai, Chris Ngai, Xumou Xu, Xumou Xu, "45nm and 32nm half-pitch patterning with 193nm dry lithography and double patterning", Proc. SPIE 6924, Optical Microlithography XXI, 692421 (7 March 2008); doi: 10.1117/12.772260; https://doi.org/10.1117/12.772260

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