As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased
proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a
small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for
semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc.
can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing
implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal
layers were chosen as the target design. The process development project starts from the wafer exposure scheme
setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the
process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical
The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure
parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and
DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have
examined the immersion process defect impact and control methodology for production environment. In this paper,
we report the result of optimizing RET process (including mask data generation, reticle making specifications, and
wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it
is capable of meeting 32nm SRAM manufacturing requirement.