7 March 2008 Evaluation of inverse lithography technology for 55nm-node memory device
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Abstract
Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.
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Byung-ug Cho, Sung-woo Ko, Jae-seung Choi, Cheol-Kyun Kim, Hyun-jo Yang, DongGyu Yim, David Kim, Bob Gleason, KiHo Baik, Ying Cui, Thuc Dam, Linyong Pang, "Evaluation of inverse lithography technology for 55nm-node memory device", Proc. SPIE 6924, Optical Microlithography XXI, 692438 (7 March 2008); doi: 10.1117/12.772515; https://doi.org/10.1117/12.772515
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