Various resolution enhancement techniques have been proposed in order to enable optical lithography
at low k1 imaging, e.g. alt-PSM (phase shift mask), chromeless phase lithography (CPL), double
exposure technique (DET) and double dipole lithography (DDL). In spite of its low throughput in
production, DDL technique is a very attractive solution for low k1 process because of the relatively low
cost of binary or attenuated phase shift masks, which can be combined with strong dipole illuminations
and flexible SRAF rule to enhance the process window. Another attraction of DDL is that dry scanner
still can be used for 45nm node instead of expensive immersion lithography process.
In this paper, two aspects for DDL application have been focused on. The first one is OPC optimization
method for DDL, which includes SRAF optimization, mask decomposition and pixel-based OPC. The
whole flow is optimized specifically for DDL to achieve satisfactory pattern results on wafer. The
second is the overlay issue. Since two DDL masks are exposed in turn, the overlay variation between
two masks becomes dominant factor deteriorating pattern quality. The effect of overlay tolerance is also
studied through process window simulation.
DDL has been demonstrated to be capable of 45nm node logic with dry scanner. The pattern fidelity and
process window of 45nm node SRAM & Random Logic are evaluated for active/gate layer and dark
field metal layer.