1 April 2008 Resolution enhancement techniques in 65 nm node nested-hole patterning
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In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process, regarding porcess cost redcution and easy access to RETs.
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Hyesung Lee, Jaeyoung Choi, Jeahee Kim, Jaewon Han, Keun-Young Kim, "Resolution enhancement techniques in 65 nm node nested-hole patterning", Proc. SPIE 6924, Optical Microlithography XXI, 69244B (1 April 2008); doi: 10.1117/12.773017; https://doi.org/10.1117/12.773017

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