1 April 2008 Resolution enhancement techniques in 65 nm node nested-hole patterning
Author Affiliations +
Proceedings Volume 6924, Optical Microlithography XXI; 69244B (2008); doi: 10.1117/12.773017
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States
In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process, regarding porcess cost redcution and easy access to RETs.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hyesung Lee, Jaeyoung Choi, Jeahee Kim, Jaewon Han, Keun-Young Kim, "Resolution enhancement techniques in 65 nm node nested-hole patterning", Proc. SPIE 6924, Optical Microlithography XXI, 69244B (1 April 2008); doi: 10.1117/12.773017; https://doi.org/10.1117/12.773017

Nanoimprint lithography

Resolution enhancement technologies

Optical lithography


Critical dimension metrology

Diffractive optical elements

Photoresist processing

Back to Top