In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor
device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled
CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement
factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic
fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance
of the device.
Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield.
TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator
(UTB FD-SOI) nMOSFET, with a physical gate length of 32 nm. Electrical parameters such as on- and off-
current, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and
extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed
and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior
of the device.
In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of
interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters
and transferring them from one program to the other are explained, and further automation capabilities
are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device
process optimization procedure.