Global and local factors of on-chip variation of gate length

Morimi Osawa; Koji Hosono; Satoru Asai

doi:10.1117/12.772568

4 March 2008 Global and local factors of on-chip variation of gate length

Morimi Osawa, Koji Hosono, Satoru Asai

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 692508 (2008) https://doi.org/10.1117/12.772568
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

For accurate analysis of circuit performance, an understanding on-chip gate length variation is required. Non-systematic OCLV was measured by SEM and the results were analyzed after being divided into local and global factors. Simple empirical models of global and local variations were proposed, and fitting was done. In the fitting, measured mask variation was used, and on-chip variation of focus, dose, and LWR were fitting parameters. The fit of our model was very consistent with experimental result. Prediction of global and local variation using lithographic characters of patterns, such as EL, DOF, and MEEF, was enabled.

Citation Download Citation

Morimi Osawa, Koji Hosono, and Satoru Asai "Global and local factors of on-chip variation of gate length", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692508 (4 March 2008); https://doi.org/10.1117/12.772568

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