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19 March 2008 Context analysis and validation of lithography induced systematic variations in 65nm designs
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The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a real design.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Arjun Rajagopal, Anand Rajaram, Raguram Damodaran, Frank Cano, Srinivas Swaminathan, Clive Bittlestone, Mark Terry, Mark Mason, Yajun Ran, Haizhou Chen, Robert Ritchie, Bala Kasthuri, Jac Condella, Philippe Hurat, and Nishath Verghese "Context analysis and validation of lithography induced systematic variations in 65nm designs", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250A (19 March 2008);

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