12 March 2008 Low k1 logic design using gridded design rules
Author Affiliations +
Abstract
Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela CanvasTM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael C. Smayling, Michael C. Smayling, Hua-yu Liu, Hua-yu Liu, Lynn Cai, Lynn Cai, } "Low k1 logic design using gridded design rules", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250B (12 March 2008); doi: 10.1117/12.772875; https://doi.org/10.1117/12.772875
PROCEEDINGS
7 PAGES


SHARE
RELATED CONTENT

Double-patterning-friendly OPC
Proceedings of SPIE (March 16 2009)
Hurdles in low k1 mass production
Proceedings of SPIE (May 11 2004)
Solutions for 22-nm node patterning using ArFi technology
Proceedings of SPIE (April 05 2011)
Improved CD control for 45 40 nm CMOS logic patterning...
Proceedings of SPIE (April 01 2010)

Back to Top