4 March 2008 Layout optimization based on a generalized process variability model
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The growing impact of process variation on circuit performance requires statistical design approaches in which circuits are designed and optimized subject to an estimated variation. Previous work [1] has explicitly accounted for variation and spatial correlations by including extra margins in each of the gate delay and correlation factor between path delays. However, as it is recently shown, what is often referred to as "spatial correlation" is an artifact of un-modeled residuals after the decomposition of deterministic variation components across the wafer and across the die [2]. Consequently, a more accurate representation of process variability is to introduce these deterministic variability components in the model, and therefore generate any apparent spatial correlation as the artifact of those deterministic components, just like in the actual process. This approach is used to re-size an 8-bit Ladner-Fischer adder. The optimized circuit delay distribution is obtained from Monte Carlo simulations. A layout generation tool is also being constructed to incorporate the optimization procedure into the standard design flow. Custom circuit layouts are first subjected to design rules to extract constraints that specify the margins allowed for each transistor active area edge movement. Sizing optimization is then performed with design rule constraints taken into account. A new circuit layout is generated based on the optimization results and checked to ensure DRC cleanness. The optimized layout can be subjected to further verification such as hotspot detection to account for any additional layout dependant effects.
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Qian Ying Tang, Qian Ying Tang, Costas J. Spanos, Costas J. Spanos, } "Layout optimization based on a generalized process variability model", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250F (4 March 2008); doi: 10.1117/12.772882; https://doi.org/10.1117/12.772882

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