With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be
ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS
technologies is the gate length (Lgate) of a transistor. In modern technologies, significant spatial intra-chip variability of
transistor gate lengths, which is systematic as opposed to random, can lead to relatively large variations in circuit path
delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss.
To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing
analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of
our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and
maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper, we
describe the chip timing methodology, its validation and implementation in microprocessor design.