At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D
image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules
constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow
development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic
designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the
manufacturability of their layouts because of the lack of understanding of the litho process.
Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window.
These rules are usually derived from lithographic models. Direct validation of AF rules is required at development
phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes
were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also
lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically
optimize performance of recipe bearing all these variables in mind.
In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are
generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment
gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full
process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from
simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the
assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for
contact coverage, etc.
Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR
evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also
offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist
features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature
critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based
on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly
used method of least intensity variation.