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2 May 2008 Design trade-offs in ADC architectures dedicated to uncooled focal plane arrays
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This paper presents two different architectures for the design of Analog to Digital Converters specifically adapted to infrared bolometric image sensors. Indeed, the increasing demand for integrated functions in uncooled readout circuits leads to on-chip ADC design as an interface between the internal analog core and the digital processing electronics. However specifying an on-chip ADC dedicated to focal plane array raises many questions about its architecture and its performance requirements. We will show that two architecture approaches are needed to cover the different sensor features in terms of array size and frame speed. A monolithic 14 bits ADC with a pipeline architecture, and a column 13 bits ADC with an original dual-ramp architecture, will be described. Finally, we will show measurement results to confirm the monolithic ADC is suitable for small array, as 160 x 120 with low frame speed, while a column ADC is more compliant for higher array, as 640 x 480 with a 60 Hz frame speed or 1024 x 768 arrays.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
P. Robert, B. Dupont, and D. Pochic "Design trade-offs in ADC architectures dedicated to uncooled focal plane arrays", Proc. SPIE 6940, Infrared Technology and Applications XXXIV, 69401U (2 May 2008);

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