The CMOS silicon focal plan array technologies hybridized with infrared detectors materials allow to cover a wide
range of applications in the field of space, airborne and
grounded-based imaging. Regarding other industries which are
also using embedded systems, the requirements of such sensor assembly can be seen as very similar; high reliability, low
weight, low power, radiation hardness for space applications and cost reduction. Comparing to CCDs technology,
excepted the fact that CMOS fabrication uses standard commercial semiconductor foundry, the interest of this
technology used in cooled IR sensors is its capability to operate in a wide range of temperature from 300K to cryogenic
with a high density of integration and keeping at the same time good performances in term of frequency, noise and power
The CMOS technology roadmap predict aggressive scaling down of device size, transistor threshold voltage, oxide and
metal thicknesses to meet the growing demands for higher levels of integration and performance.
At the same time infrared detectors manufacturing process is developing IR materials with a tunable cut-off wavelength
capable to cover bandwidths from visible to 20μm. The requirements of third generation IR detectors are driving to
scaling down the pixel pitch, to develop IR materials with high uniformity on larger formats, to develop Avalanche
Photo Diodes (APD) and dual band technologies.
These needs in IR detectors technologies developments associated to CMOS technology, used as a readout
element, are offering new capabilities and new opportunities for cooled infrared FPAs. The exponential increase of new
functionalities on chip, like the active 2D and 3D imaging, the on chip analog to digital conversion, the signal processing
on chip, the bicolor, the dual band and DTI (Double Time Integration) mode ...is aiming to enlarge the field of
application for cooled IR FPAs challenging by the way the design activity.