Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit
for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor
techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with
these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This
limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically
amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it
adversely affects device speed and timing in CMOS circuits.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This
technology has been shown to be an effective method for replication of nanometer-scale structures from a template
(imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the
ability to create a master template having the required dimensions.
Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of
minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are
not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of
this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final
Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On
average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.