17 October 2008 Challenges for the quality control of assist features for 45nm node technology and beyond
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Current flash memory technology is facing more and more challenges for 45nm and 32nm node technology. To get good CD and yield control, optimized RET, OPC modeling and DFM techniques have to be applied [1]. To enhance process window (PW) and better CD control for main features, assist features (SB) have to be used. Simulation and wafer evaluation show that the SB CD performance is very critical. Based on OPC simulation, we can get a very good prediction about the CD size and placement of assist features. However, we can not always get what we want from mask suppliers. For 45nm node technology and beyond, The SB CD size (~ 20nm at 1X) has almost pushed to the current mask process limit. Wafer fabs have a very big concern about the stability of linearity signatures from different suppliers and different products in order to keep high accuracy of OPC models. Actually the CD linearity signature varies from one mask supplier to another and also varies from product to product. To improve the SB CD control, the ideal goal is to make "flat" linearity for all mask suppliers. By working closely with TPI mask supplier, we come up solutions to improve SB CD control to get "flat" linearity. Also technology development is causing more severe SB printability, we proposed a methodology to use AIMS for predicting SB printability. Wafer results proved the feasibility for these methodologies.
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Lin Wang, Todd Lukanc, Makoto Takahashi, Hung-Eil Kim, Khoi Phan, Taichi Yamazaki, Yosuke Kojima, Wataru Nozaki, Takashi Haraguchi, Yoshimitsu Okuda, "Challenges for the quality control of assist features for 45nm node technology and beyond", Proc. SPIE 7122, Photomask Technology 2008, 71220Z (17 October 2008); doi: 10.1117/12.800916; https://doi.org/10.1117/12.800916


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