Reticle cost and cycle time to deliver new circuit designs to a wafer fab remain key focus areas for advanced
semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity
correction as applied to critical layers have increased the burden on mask data preparation and reticle writing steps of the
mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle
in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength
exposure in extremely low k1 lithography exacerbates the underlying trends.
Two important factors come together to drive the economics and performance of the reticle line: the complexity of the
designs and the productivity of e-beam writing tools. The designs, OPC methods, and writing tool capabilities continue
to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity
across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput
testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary
Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability
by introducing new quantitative methods, benchmarking metrics, and testing strategies. The findings are projected into
the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or
possible gaps in technology development.