Translator Disclaimer
13 October 2008 Simulation and experimental validation of substrate noise reduction techniques for power switching circuits
Author Affiliations +
Abstract
Single chip integrated power switching circuits can generate huge substrate noise, which impacts the circuit performance of noise sensitive blocks on the same chip. In this paper, the effects of several schematic and layout techniques to reduce substrate noise, including optimizing gate resistors and capacitors, merging NWELL of power devices, adding PEPI around NWELLs, using separated PADs for less noisy blocks, are validated by both simulation and silicon experiments.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jian Yang, Hongwei Zhao, Iven Zheng, Tommy Mao, Weiying Li, and Richard Wang "Simulation and experimental validation of substrate noise reduction techniques for power switching circuits", Proc. SPIE 7127, Seventh International Symposium on Instrumentation and Control Technology: Sensors and Instruments, Computer Simulation, and Artificial Intelligence, 71271M (13 October 2008); https://doi.org/10.1117/12.806572
PROCEEDINGS
5 PAGES


SHARE
Advertisement
Advertisement
Back to Top