4 December 2008 Patterning performance of hyper NA immersion lithography for 32nm node logic process
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Proceedings Volume 7140, Lithography Asia 2008; 714017 (2008) https://doi.org/10.1117/12.804739
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan
Abstract
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
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Kazuhiro Takahata, Masanari Kajiwara, Yosuke Kitamura, Tomoko Ojima, Masaki Satake, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyo, Akiko Nomachi, Hideaki Harakawa, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Shoji Mimotogi, Soichi Inoue, "Patterning performance of hyper NA immersion lithography for 32nm node logic process", Proc. SPIE 7140, Lithography Asia 2008, 714017 (4 December 2008); doi: 10.1117/12.804739; https://doi.org/10.1117/12.804739
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