Patterning performance of hyper NA immersion lithography for 32nm node logic process

Kazuhiro Takahata; Masanari Kajiwara; Yosuke Kitamura; Tomoko Ojima; Masaki Satake; Hiroharu Fujise; Yuriko Seino; Tatsuhiko Ema; Manabu Takakuwa; Shinichiro Nakagawa; Takuya Kono; Masafumi Asano; Suigen Kyo; Akiko Nomachi; Hideaki Harakawa; Tatsuya Ishida; Shunsuke Hasegawa; Katsura Miyashita; Takashi Murakami; Seiji Nagahara; Kazuhiro Takeda; Shoji Mimotogi; Soichi Inoue

doi:10.1117/12.804739

Translator Disclaimer

4 December 2008 Patterning performance of hyper NA immersion lithography for 32nm node logic process

Kazuhiro Takahata; Masanari Kajiwara; Yosuke Kitamura; Tomoko Ojima; Masaki Satake; Hiroharu Fujise; Yuriko Seino; Tatsuhiko Ema; Manabu Takakuwa; Shinichiro Nakagawa; Takuya Kono; Masafumi Asano; Suigen Kyo; Akiko Nomachi; Hideaki Harakawa; Tatsuya Ishida; Shunsuke Hasegawa; Katsura Miyashita; Takashi Murakami; Seiji Nagahara; Kazuhiro Takeda; Shoji Mimotogi; Soichi Inoue

Author Affiliations +

Proceedings Volume 7140, Lithography Asia 2008; 714017 (2008) https://doi.org/10.1117/12.804739
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan

Abstract

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Citation Download Citation

Kazuhiro Takahata, Masanari Kajiwara, Yosuke Kitamura, Tomoko Ojima, Masaki Satake, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyo, Akiko Nomachi, Hideaki Harakawa, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Shoji Mimotogi, and Soichi Inoue "Patterning performance of hyper NA immersion lithography for 32nm node logic process", Proc. SPIE 7140, Lithography Asia 2008, 714017 (4 December 2008); https://doi.org/10.1117/12.804739

PROCEEDINGS
10 PAGES

DOWNLOAD PDF SAVE TO MY LIBRARY

SHARE

GET CITATION

< Previous Article

|

Next Article >

KEYWORDS

Resolution enhancement technologies

Optical lithography

Lithography

Logic

Metals

SRAF

Immersion lithography

Show All Keywords

RELATED CONTENT

Model-based pattern dummy generation for logic devices
Proceedings of SPIE (March 31 2014)

Layer aware source mask target optimization
Proceedings of SPIE (March 15 2016)

Early stage hot spot analysis through standard cell base random...
Proceedings of SPIE (April 04 2017)

22nm logic lithography in the presence of local interconnect
Proceedings of SPIE (March 03 2010)

A generic method for the detection of electrically superfluous layout...
Proceedings of SPIE (October 20 2006)

Feasibility of ultra-low k1 lithography for 28nm CMOS node
Proceedings of SPIE (March 16 2009)

Full-chip single exposure vortex mask for contact/via
Proceedings of SPIE (May 12 2005)

Subscribe to Digital Library

Receive Erratum Email Alert

Show All Keywords

Keywords/Phrases

Search In:

Publication Years