In an effort to keep scaling at the speed of Moores law, novel methods are being developed to facilitate advanced semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches beyond the current lithography resolution limit is spacer pitch splitting. This method typically involves patterning a sacrificial gate pattern, then performing a standard spacer deposition and etch back process, after which the sacrificial gate is removed and the remaining spacers themselves are used as the effective mask for the pattern transfer. Some of the key advantages of this process are the ability to create sub-resolution lines and also the improvement in Line Edge Roughness seen on the final pattern. However, there are certain limitations with this process, namely the ability to only pattern lines in one dimension, and also the complexity of the metrology, where the final Critical Dimension result is a function of the litho condition from the sacrificial gate patterning, and also the various film layer depositions as well as the spacer etch back process. Given this complexity, the accurate measurement of not only the spacer width but also the spacer shape is important. In this work we investigate the use of scatterometry techniques to enable these measurements on leading edge devices.