4 December 2008 Throughput improvement from routing reduction by using CPE (correction per exposure)
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Proceedings Volume 7140, Lithography Asia 2008; 714043 (2008) https://doi.org/10.1117/12.806643
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan
Abstract
The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE). We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.
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Ray C. Chang, Jui-Chin Yang, Chia-Hung Chen, Chi-Chun Lin, Cathy Wang, Wythe Lin, Chia-Chi Chen, "Throughput improvement from routing reduction by using CPE (correction per exposure)", Proc. SPIE 7140, Lithography Asia 2008, 714043 (4 December 2008); doi: 10.1117/12.806643; https://doi.org/10.1117/12.806643
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