4 February 2009 Iris matching with configurable hardware
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Abstract
Iris recognition systems have recently become an attractive identification method because of their extremely high accuracy. Most modern iris recognition systems are currently deployed on traditional sequential digital systems, such as a computer. However, modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. In this study, iris matching, a repeatedly executed portion of a modern iris recognition algorithm is parallelized on an FPGA system. We demonstrate a 19 times speedup of the parallelized algorithm on the FPGA system when compared to a state-of-the-art CPU-based version.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ryan N. Rakvic, Ryan N. Rakvic, Randy P. Broussard, Randy P. Broussard, Delores Etter, Delores Etter, Lauren Kennell, Lauren Kennell, Jim Matey, Jim Matey, "Iris matching with configurable hardware", Proc. SPIE 7244, Real-Time Image and Video Processing 2009, 724402 (4 February 2009); doi: 10.1117/12.805963; https://doi.org/10.1117/12.805963
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