We present the design and we discuss in depth the operating conditions of a two-dimensional (2-D) imaging array of
single-photon detectors that provides a total of 1024 pixels, laid out in 32 rows by 32 columns array, integrated within a
monolithic silicon chip with dimensions of 3.5 mm x 3.5 mm. We employed a standard high-voltage 0.35μm CMOS
fabrication technology, with no need of any custom processing.
Each pixel consists of one Single-Photon Avalanche Diode (SPAD) and a compact front-end analog electronics followed
by a digital processing circuitry. The in-pixel front-end electronics senses the ignition of the avalanche, quenches the
detector, provides a pulse and restores the detector for detecting a subsequent photon. The processing circuitry counts
events (both photon and unwelcome "noise" ignition) within user-selectable integration time-slots and stores the count
into an in-pixel memory cell, which is read-out in 10 ns/pixel. Such a two-levels pipeline architecture allows to acquire the actual frame while contemporary reading out the previous one, thus achieving a very high free-running frame rate, with negligible inter-frame dead-time. Each pixel is therefore a completely independent photon-counter. The measured Photo Detection Efficiency (PDE) tops 43% at 5V excess-bias, while the Dark-Counting Rate (DCR) is below 4kcps (counts per second) at room temperature. The maximum frame-rate depends on the system clock; with a convenient 100MHz system clock we achieved a free-running speed of 100 kframe/s from the all 1024 pixels.