30 December 2008 High-performance bridge-style full adder structure
Author Affiliations +
Abstract
Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Omid Kavehei, Omid Kavehei, Said F. Al-Sarawi, Said F. Al-Sarawi, Derek Abbott, Derek Abbott, Keivan Navi, Keivan Navi, } "High-performance bridge-style full adder structure", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680D (30 December 2008); doi: 10.1117/12.813924; https://doi.org/10.1117/12.813924
PROCEEDINGS
9 PAGES


SHARE
RELATED CONTENT

A New Miniature Fabry-Perot Wavelength Demultiplexer
Proceedings of SPIE (September 22 1987)
Methodology for optimizing transistor performance
Proceedings of SPIE (August 27 1997)
Sub 5.5 FO4 delay CMOS 64 bit domino threshold logic...
Proceedings of SPIE (March 30 2004)
Defect tolerant prefix adder design
Proceedings of SPIE (December 30 2008)

Back to Top