30 December 2008 Self-aligned double-gate (DG) vertical nanoscale MOSFETs with reduced parasitic capacitance
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Abstract
Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while having a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.
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Razali Ismail, Razali Ismail, Ismail Saad, Ismail Saad, } "Self-aligned double-gate (DG) vertical nanoscale MOSFETs with reduced parasitic capacitance", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680U (30 December 2008); doi: 10.1117/12.814129; https://doi.org/10.1117/12.814129
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