17 March 2009 Integration of EUV lithography in the fabrication of 22-nm node devices
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Abstract
On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.
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Obert Wood, Chiew-Seng Koay, Karen Petrillo, Hiroyuki Mizuno, Sudhar Raghunathan, John Arnold, Dave Horak, Martin Burkhardt, Gregory McIntyre, Yunfei Deng, Bruno La Fontaine, Uzodinma Okoroanyanwu, Anna Tchikoulaeva, Tom Wallow, James H.-C. Chen, Matthew Colburn, Susan S.-C. Fan, Bala S. Haran, Yunpeng Yin, "Integration of EUV lithography in the fabrication of 22-nm node devices", Proc. SPIE 7271, Alternative Lithographic Technologies, 727104 (17 March 2009); doi: 10.1117/12.814379; https://doi.org/10.1117/12.814379
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