23 March 2009 Sampling for advanced overlay process control
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Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 727206 (2009); doi: 10.1117/12.813568
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States
Abstract
Overlay metrology and control have been critical for successful advanced microlithography for many years, and are taking on an even more important role as time goes on. Due to throughput constraints it is necessary to sample only a small subset of overlay metrology marks, and typical sample plans are static over time. Standard production monitoring and control involves measuring sufficient samples to calculate up to 6 linear correctables. As design rules shrink and processing becomes more complex, however, it is necessary to consider higher order models with additional degrees of freedom for control, fault detection, and disposition. This in turn, requires a higher level of sampling and a careful consideration of flyer removal. Due to throughput concerns, however, careful consideration is needed to establish a baseline sampling plan using rigorous statistical methods. This study focuses on establishing a 3x nm node immersion lithography production-worthy sampling plan for 3rd order modeling, verification of the accuracy, and proof of robustness of the sampling. In addition we discuss motivation for dynamic sampling for application to higher order modeling.
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Cindy Kato, Hiroyuki Kurita, Pavel Izikson, John C. Robinson, "Sampling for advanced overlay process control", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 727206 (23 March 2009); doi: 10.1117/12.813568; https://doi.org/10.1117/12.813568
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KEYWORDS
Semiconducting wafers

Overlay metrology

Process control

Monte Carlo methods

Time metrology

Control systems

Optical lithography

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