23 March 2009 Intrafield process control for 45 nm CMOS logic patterning
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Abstract
CMOS 45nm technology, and especially the logic gate patterning has led us to hunt for every nanometer we could found to reach aggressive targets in term of overall CD budget. We have presented last year a paper ("Process Control for 45 nm CMOS logic gate patterning " - B. Le Gratiet SPIE2008; 6922-33) showing the evaluation of our process at that time. One of the key item was the intrafield control. Preliminary data were presented regarding intrafield CD corrections using Dose MapperTM. Since then, more work has been done in this direction and not only for the GATE level. Depending on reticle specification grade, process MEEF and scanner performance, intrafield CD variation can reach quite high CD ranges and become a non negligeable part of the overall budget. Although reticles can achieve very good level of CD uniformity, they all have their own "footprint" which will becomes a systematic error. The key point then is to be able to measure this footprint and correct for it on the wafer. Scanners suppliers provide tools like Dose MapperTM to modify the intrafield exposure dose profile. Generating and using a proper exposure "subrecipe" requires intrafield in-line control needs on production wafers. This paper present a status of our work on this subject with some results related to global gate CMOS 45nm CD variability improvement including etch process compensation with Dose Mapper.
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Bertrand Le Gratiet, Bertrand Le Gratiet, Jean Massin, Jean Massin, Alain Ostrovski, Alain Ostrovski, Cedric Monget, Cedric Monget, Marianne Decaux, Marianne Decaux, Nicolas Thivolle, Nicolas Thivolle, Romuald Faure, Romuald Faure, Fabrice Baron, Fabrice Baron, Jean-Damien Chapon, Jean-Damien Chapon, Karen Dabertrand, Karen Dabertrand, Frank Sundermann, Frank Sundermann, Pascal Gouraud, Pascal Gouraud, Laurène Babaud, Laurène Babaud, Lionel Thevenon, Lionel Thevenon, Nicolas Cluet, Nicolas Cluet, Boris VandeWalle, Boris VandeWalle, } "Intrafield process control for 45 nm CMOS logic patterning", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72722P (23 March 2009); doi: 10.1117/12.812571; https://doi.org/10.1117/12.812571
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