23 March 2009 Efficient use of design-based binning methodology in a DRAM fab
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Abstract
It is a well established fact that as design rules and printed features shrink, sophisticated techniques are required to ensure the design intent is indeed printed on the wafer. Techniques of this kind are Optical Proximity Correction (OPC), Resolution Enhancement Techniques (RET) and DFM Design for Manufacturing (DFM). As these methods are applied to the overall chip and rely on complex modeling and simulations, they increase the risk of creating local areas or layouts with a limiting process window. Hence, it is necessary to verify the manufacturability (sufficient depth of focus) of the overall die and not only of a pre-defined set of metrology structures. The verification process is commonly based on full chip defect density inspection of a Focus Exposure Matrix (FEM) wafer, combined with appropriate post processing of the inspection data. This is necessary to avoid time consuming search for the Defects of Interest (DOI's) as defect counts are usually too high to be handled by manual SEM review. One way to post process defect density data is the so called design based binning (DBB). The Litho Qualification Monitor (LQM) system allows to classify and also to bin defects based on design information. In this paper we will present an efficient way to combine classification and binning in order to check design rules and to determine the marginal features (layout with low depth of focus). The Design Based Binning has been connected to the Yield Management System (YMS) to allow new process monitoring approaches towards Design Based SPC. This could dramatically cut the time to detect systematic defects inline.
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Laurent Karsenti, Laurent Karsenti, Arno Wehner, Arno Wehner, Andreas Fischer, Andreas Fischer, Uwe Seifert, Uwe Seifert, Jens Goeckeritz, Jens Goeckeritz, Mark Geshel, Mark Geshel, Dieter Gscheidlen, Dieter Gscheidlen, Avishai Bartov, Avishai Bartov, } "Efficient use of design-based binning methodology in a DRAM fab", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 727239 (23 March 2009); doi: 10.1117/12.814095; https://doi.org/10.1117/12.814095
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