In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into
one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying
stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate
reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography
and is required in order to meet their aggressive requirements for developing 32nm technology and beyond.
The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on
topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability
of dBARC as a working solution for block level lithography.1 Wet-developable BARC by definition offers substrate
reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the
dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating
adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be
envisioned as most imminent dBARC applications.2 However, most of the engineering community is still indecisive to
use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production.
This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe
testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices.
The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process,
with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages
and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have
shallow trench isolation (STI) and poly gate pattern topography.