CD and defect improvement challenges for immersion processes

Keisuke Ehara; Tatsuhiko Ema; Toshinari Yamasaki; Seiji Nakagawa; Seiji Ishitani; Akihiko Morita; Jeonghun Kim; Masashi Kanaoka; Shuichi Yasuda; Masaya Asai

doi:10.1117/12.814234

1 April 2009 CD and defect improvement challenges for immersion processes

Keisuke Ehara, Tatsuhiko Ema, Toshinari Yamasaki, Seiji Nakagawa, Seiji Ishitani, Akihiko Morita, Jeonghun Kim, Masashi Kanaoka, Shuichi Yasuda, Masaya Asai

Author Affiliations +

Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 727322 (2009) https://doi.org/10.1117/12.814234
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

Citation Download Citation

Keisuke Ehara, Tatsuhiko Ema, Toshinari Yamasaki, Seiji Nakagawa, Seiji Ishitani, Akihiko Morita, Jeonghun Kim, Masashi Kanaoka, Shuichi Yasuda, and Masaya Asai "CD and defect improvement challenges for immersion processes", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 727322 (1 April 2009); https://doi.org/10.1117/12.814234

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